In Document 1 (JP2005-26589), a semiconductor memory device and a manufacturing method thereof that make it possible to make a gate insulating film of a peripheral circuit portion thinner than a gate insulating film of a cell portion and miniaturize select transistors in the memory cell column are disclosed.
In Document 2 (JP2006-73939), a nonvolatile semiconductor memory device having a plurality of memory cell transistors arranged in a matrix form above an insulating layer is described. In Document 2, each memory cell transistor is a depletion MIS transistor having source and drain regions of a first conductivity type that are opposed to each other and arranged above the insulating layer, a channel region of the first conductivity type disposed between the source and drain regions and having an impurity concentration lower than the source and drain regions, a floating gate electrode insulatively arranged above the channel region and a control gate electrode insulatively arranged above the floating gate electrode.
Conventionally, when a value stored in a memory cell having the floating gate and control gate is read in a nonvolatile semiconductor memory device such as a NAND flash memory, for example, a select gate transistor provided for the memory cell is turned on and the value stored in the memory cell is determined based on a state in which the potential of the memory cell is propagated or not.
In the conventional planar type select gate transistor, the controllability of the select gate transistor may be degraded because of shortening of a channel length, the resistance may be made high because of an effect of a channel width, the drivability may be reduced and the selectivity may be degraded. In such a case, it may become difficult to sense the memory cell.